Article 12
Morgan Stanley among first banks to tokenize US equities, Treasurys through DTCC’s service
TL;DR
Morgan Stanley has begun tokenizing U.S. equities and Treasurys via the Depository Trust & Clearing Corporation's new digital asset infrastructure. This move places the bank alongside other global financial giants participating in the early stages of real-world asset tokenization.
Morgan Stanley has officially announced its participation in the Depository Trust & Clearing Corporation's (DTCC) newly launched tokenization service, marking a significant step in the integration of digital assets with traditional market infrastructure. By utilizing this service, the bank is now able to tokenize U.S. equities and Treasurys, positioning itself as an early adopter of real-world asset (RWA) tokenization technology. This initiative is part of a broader industry movement, as DTCC's depository subsidiary, DTC, launched the service with 20 initial participants including Bank of America, Barclays, BNP Paribas, Citi, Fidelity Investments, JPMorgan, State Street, and UBS. The infrastructure itself was developed through extensive collaboration with over 150 firms and leverages the Canton network and its private Besu network. While Morgan Stanley is advancing its digital asset capabilities, it has adjusted its timeline for supporting tokenized equities on its alternative trading system to the first quarter of 2027. The competitive landscape for tokenization is expanding rapidly, with the New York Stock Exchange and Intercontinental Exchange also developing tokenized trading platforms, supported by transfer agents such as Broadridge, Computershare, Equiniti, and Superstate.
DTCC Tokenization Service
Canton
Hyperledger Besu
DTC (Depository Trust Company)
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Article 13
New lattice assumption, LAR, links rounding to quantum-resistant encryption
TL;DR
Researchers have developed the Learning with Algebraic Rounding (LAR) assumption, a breakthrough in lattice-based cryptography that utilizes deterministic rounding. This new approach enables post-quantum security using fixed polynomial parameters, bypassing the need for pre-defined sample bounds required by previous methods.
The research presented by Chen Qian of Shandong University introduces the Learning with Algebraic Rounding (LAR) assumption, a significant advancement in the field of post-quantum cryptography. Unlike traditional Learning with Rounding (LWR) techniques that require parameters to be tailored to specific sample bounds, LAR utilizes an algebraic rounding function (ART) to achieve pseudorandomness through deterministic information loss. This method allows for fixed polynomial parameters, which simplifies implementation and enhances efficiency in cryptographic systems.
The security of LAR is mathematically anchored in the hardness of well-known lattice problems, namely the Gap Shortest Vector Problem (GapSVP) and the Shortest Independent Vectors Problem (SIVP). By establishing a quantum reduction from Gaussian LWE to LAR, the researchers demonstrate that breaking the decisional version of LAR would be equivalent to solving these worst-case lattice problems in quantum polynomial time. This provides a robust, quantifiable security foundation that remains resilient even against adversaries with access to an infinite number of security parameters.
A key technical contribution is the use of a source-independent affine transport framework. This framework allows for the reduction of Gaussian LWE to uniform-zero-fiber LWE by using public affine maps to move Gaussian errors toward a uniform distribution on the rounding map's zero-label fiber. This process ensures that the resulting public matrices remain exactly uniform and independent of the transported error.
Beyond its cryptographic utility, the research reveals interesting connections to machine learning. The authors demonstrate that the labels produced by the algebraic rounding process can be represented as polynomial-size two-hidden-layer ReLU networks. This suggests that the hardness of distinguishing LAR pseudorandomness is intrinsically linked to the difficulty of learning from noiseless uniform random examples in neural networks, potentially offering new insights into machine learning security and robustness.
Learning with Algebraic Rounding (LAR)
Learning with Errors (LWE)
Learning with Rounding (LWR)
GapSVP
SIVP
TC^0 circuits
ReLU networks
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Article 18
Summary of the RTGS CHAPS Industry Forum - 13 October 2026
TL;DR
The Bank of England's October 2026 forum detailed strategic shifts toward extended settlement hours and the implementation of atomic synchronisation for tokenised assets. The meeting also addressed technical delays in standards releases and the necessity of robust contingency plans for systemic payment disruptions.
The RTGS CHAPS Industry Forum held on 13 October 2026 focused on several critical updates regarding the UK's high-value payment infrastructure. A primary focus was the ongoing tokenisation workplan, which involves collaboration between the Bank of England, HM Treasury, and the FCA to move from pilot programs toward live activity involving digital asset issuance and settlement in central bank money. The Bank also provided an update on extending RTGS and CHAPS settlement hours; while there is broad support for longer weekday hours, the Bank is still evaluating the sequencing for Sundays and bank holidays. Notably, work is already progressing to allow CHAPS to open at 1:30am, which is expected to impact approximately 20% of payment volumes before 6am. Another significant technical development discussed was 'synchronisation,' a functionality designed to enable atomic settlement between external asset ledgers and sterling central bank money, facilitating more efficient margin and collateral optimization. Regarding industry standards, the Bank noted that the November 2026 RTGS Standards Release has been delayed following Swift's decision to postpone its 2026 release due to challenges with removing unstructured address fields. This delay has prompted discussions regarding the potential mandate of structured addresses via the CHAPS rulebook. Finally, the forum addressed operational resilience, specifically focusing on maintaining payment processing capabilities during major outages, such as a Swift disruption, and the need for automated rather than manual contingency arrangements.
Article 20
TB 26-10 Printed Circuit Board Assembly Chip Resistor Body Cracking
TL;DR
NASA reports the discovery of ceramic body cracking in large-footprint chip resistors caused by mechanical board flexure. The bulletin provides specific assembly guidelines to prevent stress-induced failures during environmental testing.
This technical bulletin details an investigation into the failure of 2512 case size thick-film chip resistors during NASA environmental acceptance testing. While initial concerns focused on potential defects within the production lot (MIL-PRF-55342), independent analyses using optical and scanning electron microscopy (SEM) ruled out manufacturing defects and vibration-induced fatigue. Instead, the failures were characterized by transverse fractures across the short axis of the resistors, occurring during thermal cycling after vibration testing. The investigation identified several contributing mechanical factors: the placement of large components parallel to the PCB edge, excessive solder fillets extending to the top pads which create rigid stress-transfer points, and board deformation caused by bow/twist or rigid mounting to frames. To mitigate these risks, NASA recommends that engineers avoid orienting large ceramic components parallel to board edges, utilize Finite Element Analysis to verify stress margins, and strictly control solder fillet heights according to manufacturer specifications. Additionally, the bulletin suggests implementing functional thermal shock testing prior to vibration testing to ensure component integrity.
Thick-film chip resistors
Alumina substrate
Printed Circuit Board (PCB)
Scanning Electron Microscopy (SEM)
MIL-PRF-55342
Finite Element Analysis (FEA)
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